Verilog-to-Routing
latest

Quick Start

  • VTR Quick Start

Usage

  • VTR
  • FPGA Architecture Description
  • VPR
  • Parmys
  • Odin II
  • ABC
  • Tutorials
  • Utilities

Development

  • Developer Guide
    • Contribution Guidelines
    • Commit Procedures
    • Commit Messages and Structure
    • Code Formatting
    • Running Tests
    • Evaluating Quality of Result (QoR) Changes
    • Adding Tests
    • Debugging Aids
    • Speeding up the edit-compile-test cycle
    • Speeding Compilation
    • Profiling VTR
    • External Subtrees
    • Finding Bugs with Coverity
    • Release Procedures
    • Sphinx API Documentation for C/C++ Projects
    • Documenting VTR Code with Doxygen
    • Developer Tutorials
      • New Developer Tutorial
      • Timing Graph Debugging Tutorial
      • VPR UI and Graphics
    • VTR Support Resources
    • VTR License
  • VTR Change Log

Appendix

  • Contact
  • Glossary
  • Publications & References

API Reference

  • VPR API
  • VTRUTIL API
  • VPR INTERNALS
Verilog-to-Routing
  • Docs »
  • Developer Guide »
  • Developer Tutorials
  • Edit on GitHub

Developer TutorialsΒΆ

  • New Developer Tutorial
    • Overview
    • Environment Setup
    • Background Reading
    • Setup VTR
    • Use VTR
    • Open the Black Box
    • Submitting Changes and Regression Testing
  • Timing Graph Debugging Tutorial
    • Generating a GraphViz DOT file of the Entire Timing Graph
    • Generating a GraphViz DOT file of a subset of the Timing Graph
    • Cross-referencing Node IDs with VPR Timing Reports
  • VPR UI and Graphics
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