-
#(comment),\\(linecontinued),*(wildcard),{}(stringescape)
- $VTR_ROOT
-
--absorb_buffer_luts
-
--acc_fac
-
--activity_file
-
--allow_unrelated_clustering
-
--alpha_clustering
-
--alpha_decay
-
--alpha_max
-
--alpha_min
-
--alpha_t
-
--analysis
-
--anneal_success_min
-
--anneal_success_target
-
--astar_fac
-
--auto
-
--balance_block_type_utilization
-
--base_cost_type
-
--bb_factor
-
--bend_cost
-
--beta_clustering
-
--circuit_file
-
--circuit_format
-
--clock_modeling
-
--cluster_seed_type
-
--clustering_pin_feasibility_filter
-
--congested_routing_iteration_threshold
-
--connection_driven_clustering
-
--const_gen_inference
-
--constant_net_method
-
--criticality_exp
-
--device
-
--disp
-
--echo_dot_timing_graph_node
-
--echo_file
-
--enable_timing_computations
-
--exit_before_pack
-
--exit_t
-
--first_iter_pres_fac
-
--fix_clusters
-
--fix_pins
-
--full_stats
-
--gen_post_implementation_merged_netlist
-
--gen_post_synthesis_netlist
-
--generate_rr_node_overuse_report
-
--graphics_commands
-
--help
-
--incremental_reroute_delay_ripup
-
--init_t
-
--initial_pres_fac
-
--inner_loop_recompute_divider
-
--inner_num
-
--max_criticality
-
--max_logged_overused_rr_nodes
-
--max_router_iterations
-
--min_incremental_reroute_fanout
-
--min_route_chan_width_hint
-
--net_file
-
--netlist_verbosity
-
--noc
-
--noc_flows_file
-
--noc_latency_constraints_weighting
-
--noc_latency_weighting
-
--noc_placement_file_name
-
--noc_placement_weighting
-
--noc_routing_algorithm
-
--noc_swap_percentage
-
--num_workers
-
--outfile_prefix
-
--pack
-
--pack_feasible_block_array_size
-
--pack_high_fanout_threshold
-
--pack_prioritize_transitive_connectivity
-
--pack_transitive_fanout_threshold
-
--pack_verbosity
-
--place
-
--place_agent_algorithm
-
--place_agent_epsilon
-
--place_agent_gamma
-
--place_agent_multistate
-
--place_agent_space
-
--place_algorithm
-
--place_bounding_box_mode
-
--place_chan_width
-
--place_cost_exp
-
--place_delay_model
-
--place_delay_model_reducer
-
--place_delay_offset
-
--place_delay_ramp_delta_threshold
-
--place_delay_ramp_slope
-
--place_effort_scaling
-
--place_file
-
--place_quench_algorithm
-
--place_reward_fun
-
--place_rlim_escape
-
--place_tsu_abs_margin
-
--place_tsu_rel_margin
-
--placer_debug_block
-
--placer_debug_net
-
--post_place_timing_report
-
--post_synth_netlist_unconn_inputs
-
--post_synth_netlist_unconn_outputs
-
--power
-
--pres_fac_mult
-
--quench_recompute_divider
-
--read_placement_delay_lookup
-
--read_router_lookahead
-
--read_rr_graph
-
--read_vpr_constraints
-
--recompute_crit_iter
-
--RL_agent_placement
-
--route
-
--route_bb_update
-
--route_chan_width
-
--route_file
-
--route_type
-
--router_algorithm
-
--router_debug_net
-
--router_debug_sink_rr
-
--router_first_iter_timing_report
-
--router_high_fanout_threshold
-
--router_init_wirelength_abort_threshold
-
--router_initial_timing
-
--router_lookahead
-
--router_max_convergence_count
-
--router_reconvergence_cpd_threshold
-
--router_update_lower_bound_delays
-
--routing_budgets_algorithm
-
--routing_failure_predictor
-
--save_graphics
-
--save_routing_per_iteration
-
--sdc_file
-
--seed
-
--sink_rr_node
-
--source_rr_node
-
--strict_checks
-
--sweep_constant_primary_outputs
-
--sweep_dangling_blocks
-
--sweep_dangling_nets
-
--sweep_dangling_primary_ios
-
--target_ext_pin_util
-
--target_utilization
-
--td_place_exp_first
-
--td_place_exp_last
-
--tech_properties
-
--terminate_if_timing_fails
-
--timing_analysis
-
--timing_driven_clustering
-
--timing_report_detail
-
--timing_report_npaths
-
--timing_report_skew
-
--timing_tradeoff
-
--two_stage_clock_routing
-
--verify_binary_search
-
--verify_file_digests
-
--version
-
--write_block_usage
-
--write_initial_place_file
-
--write_placement_delay_lookup
-
--write_router_lookahead
-
--write_rr_graph
-
--write_timing_summary
|
-
--write_vpr_constraints
-
-a
-
-adder_cin_global
-
-c
-
-check_golden
-
-clock<virtualornetlistclock>
-
-cmos_tech
-
-create_golden
-
-delete_intermediate_files
-
-delete_result_files
-
-early
-
-ending_stage
-
-exact_mults
-
-exclusive
-
-from[get_clocks<clocklistorregexes>]
-
-from[get_pins<pinlistorregexes>]
-
-group{<clocklistorregexes>}
-
-h
-
-hold
-
-j
-
-l
-
-late
-
-limit_memory_usage
-
-max
-
-min
-
-min_hard_adder_size
-
-min_hard_mult_size
-
-mults_ratio
-
-name<string>
-
-nopass
-
-odin_xml
-
-parser
-
-period<float>
-
-power
-
-s
-
-setup
-
-source
-
-starting_stage
-
-system
-
-temp_dir
-
-timeout
-
-to[get_clocks<clocklistorregexes>]
-
-to[get_pins<pinlistorregexes>]
-
-top
-
-top_module
-
-track_memory_usage
-
-use_odin_simulation
-
-valgrind
-
-vtr_prim
-
-waveform{<float><float>}
-
-yosys_script
-
<areagrid_logic_tile_area="float"/>
-
<auto_layoutaspect_ratio="float">
-
<block_typeid="int"name="unique_identifier"width="int"height="int">
-
<bufferslogical_effort_factor="float"/>
-
<cbtype="pattern">intlist</cb>
-
<chan_width_distr>content</chan_width_distr>
-
<channelchan_width_max="int"x_min="int"y_min="int"x_max="int"y_max="int"/>
-
<channelsrc="logical_router_name"dst="logical_router_name"bandwidth="float"latency_cons="float"priority="int"/>
-
<clock_networkname="string"num_inst="integer">
-
<clockC_wire="float"C_wire_per_m="float"buffer_size={"float"|"auto"}/>
-
<clockname="string"num_pins="int"equivalent="{none|full}"/>
-
<coltype="string"priority="int"startx="expr"repeatx="expr"starty="expr"incry="expr"/>
-
<completename="string"input="string"output="string"/>
-
<complexblocklist>content</complexblocklist>
-
<connection_blockinput_switch_name="string"/>
-
<cornerstype="string"priority="int"/>
-
<default_fcin_type="{frac|abs}"in_val="{int|float}"out_type="{frac|abs}"out_val="{int|float}"/>
-
<delay>
-
<delay_constantmax="float"min="float"in_port="string"out_port="string"/>
-
<delay_matrixtype="{max|min}"in_port="string"out_port="string">matrix</delay>
-
<device>content</device>
-
<directfrom="string"to="string">
-
<directname="string"from_pin="string"to_pin="string"x_offset="int"y_offset="int"z_offset="int"switch_name="string"/>
-
<directname="string"input="string"output="string"/>
-
<dynamic_powerpower_per_instance="float"C_internal="float"/>
-
<edgesrc_node="int"sink_node="int"switch_id="int"/>
-
<equivalent_sites>
-
<fc_overridefc_type="{frac|abs}"fc_val="{int|float}",port_name="{string}"segment_name="{string}">
-
<fcin_type="{frac|abs}"in_val="{int|float}"out_type="{frac|abs}"out_val="{int|float}">
-
<filltype="string"priority="int"/>
-
<fixed_layoutname="string"width="int"height="int">
-
<fromtype="string"switchpoint="int,int,int,..."/>
-
<functype="string"formula="string"/>
-
<grid_locx="int"y="int"block_type_id="int"width_offset="int"height_offset="int">
-
<inputname="string"num_pins="int"equivalent="{none|full}"is_non_clock_global="{true|false}"/>
-
<latency>
-
<layerdie="int">
-
<layerdie='int'>content</layer>
-
<layout/>
-
<local_interconnectC_wire="float"factor="float"/>
-
<locside="{left|right|bottom|top}"xoffset="int"yoffset="int">name_of_complex_logic_block.port_name[int:int]...</loc>
-
<locxlow="int"ylow="int"xhigh="int"yhigh="int"side="{LEFT|RIGHT|TOP|BOTTOM}"ptc="int">
-
<metadata>
-
<metal_layername="string"Rmetal="float"Cmetal="float"/>
-
<metaname="string">
-
<modename="string"disable_packing="bool">
-
<muxname="string"/>
-
<muxname="string"input="string"output="string"/>
-
<netlistclocklistorregexes>
-
<noclink_bandwidth="float"link_latency="float"router_latency="float"noc_router_tile_name="string">
-
<noclink_bandwidth="float"link_latency="float"router_latency="float"noc_router_tile_name="string">content</noc>
-
<nodeid="int"type="unique_type"direction="unique_direction"capacity="int">
-
<opin_switchname="string"/>
-
<outputname="string"num_pins="int"equivalent="{none|full|instance}"/>
-
<pack_patternname="string"in_port="string"out_port="string"/>
-
<path_multiplier>
-
<pb_typename="string"num_pb="int"blif_model="string"/>
-
<perimetertype="string"priority="int"/>
-
<pin_classtype="pin_type">
-
<pinlocationspattern="{spread|perimeter|custom}">
-
<pinptc="block_pin_index">name</pin>
-
<portname="string"energy_per_toggle="float"scaled_by_static_prob="string"scaled_by_static_prob_n="string"/>
-
<portname="string"is_clock="{0|1}clock="string"combinational_sink_ports="string1string2..."/>
-
<powermethod="string">contents</power>
-
<regiontype="string"priority="int"startx="expr"endx="exprrepeatx="expr"incrx="expr"starty="expr"endy="expr"repeaty="expr"incry="expr"/>
-
<ribmetal_layer="string"y="expr"startx="expr"endx="expr"repeatx="expr"repeaty="expr"/>
-
<routerid="int"positionx="float"positiony="float"connections="intintintint...">
-
<rowtype="string"priority="int"starty="expr"repeaty="expr"startx="expr"/>
-
<sb_loctype="{full|straight|turns|none}"xoffset="int"yoffset="int",switch_override="string">
-
<sbtype="pattern">intlist</sb>
-
<segmentaxis="{x|y}"name="unique_name"length="int"type="{bidir|unidir}"freq="float"Rmetal="float"Cmetal="float">content</segment>
-
<segmentid="int"name="unique_identifier">
-
<segmentlist>content</segmentlist>
-
<segmentsegment_id="int">
-
<singletype="string"priority="int"x="expr"y="expr"/>
-
<sitepb_type="string"pin_mapping="string"/>
-
<sizingmux_trans_size="int"buf_size="float"/>
-
<sizingR_minW_nmos="float"R_minW_pmos="float"/>
-
<spinemetal_layer="string"x="expr"starty="expr"endy="expr"repeatx="expr"repeaty="expr"/>
-
<static_powerpower_per_instance="float"/>
-
<sub_tilename"string"capacity="{int}">
-
<switch_blocktype="{wilton|subset|universal|custom}"fs="int"/>
-
<switch_pointtype="{drive|tap}"name="string"yoffset="expr"xoffset="expr"xinc="expr"yinc="expr"buffer="string">
-
<switchblock_locationspattern="{external_full_internal_straight|all|external|internal|none|custom}"internal_switch="string">
-
<switchblock_locationtype="string"/>
-
<switchblockname="string"type="string">
-
<switchfuncs>
-
<switchid="int"name="unique_identifier"type="{mux|tristate|pass_gate|short|buffer}">
-
<switchlist>content</switchlist>
-
<switchtype="{mux|tristate|pass_gate|short|buffer}"name="string"R="float"Cin="float"Cout="float"Cinternal="float"Tdel="float"buf_size="{auto|float}"mux_trans_size="float",power_buf_size="int"/>
-
<T_clock_to_Qmax="float"min="float"port="string"clock="string"/>
-
<T_holdvalue="float"port="string"clock="string"/>
-
<T_setupvalue="float"port="string"clock="string"/>
-
<tapfrom="string"to="string"locationx="expr"locationy="expr"switch="string"fc_val="float">
-
<Tdelnum_inputs="int"delay="float"/>
-
<tilename="string"capacity="int"width="int"height="int"area="float"/>
-
<tiles>content</tiles>
-
<timingR="float"C="float">
-
<timingR="float"cin="float"Cout="float"Tdel="float/>
-
<timingR_per_meter="float"C_per_meter="float">
-
<totype="string"switchpoint="int,int,int,..."/>
-
<uncertainty>
-
<wire_switchname="string"/>
-
<wireconnnum_conns="expr"from_type="string,string,string,..."to_type="string,string,string,..."from_switchpoint="int,int,int,..."to_switchpoint="int,int,int,..."from_order="{fixed|shuffled}"to_order="{fixed|shuffled}"switch_override="string"/>
-
<x_listindex="int"info="int"/><y_listindex="int"info="int"/>
-
<xdistr="{gaussian|uniform|pulse|delta}"peak="float"width="float"xpeak="float"dc="float"/>
-
<ydistr="{gaussian|uniform|pulse|delta}"peak="float"width="float"xpeak="float"dc="float"/>
-
[get_clocks<clocklistorregexes>]
-
[get_ports{<I/Olistorregexes>}]
|